The present invention relates to a semiconductor apparatus, and more particularly to a 1-transistor type DRAM driving method performing a multi-bit operation.
Generally, a semiconductor device such as DRAM is integrated on a silicon wafer. However, in a silicon wafer used in a semiconductor device, a limited thickness of several μm from the surface of the silicon wafer is used in for device operation rather than the entire silicon wafer. As a result, the remaining silicon wafer not used for the device operation increases power consumption and decreases driving speed.
Therefore, a silicon on insulator (SOI) wafer configured by forming a silicon single crystal layer having a thickness of several μm by interposing an insulating layer between silicon substrates has been called for. A semiconductor device integrated on the SOI wafer has been shown to increase speed due to a small junction capacity thereof and can satisfy high-speed and low-voltage operation due to a low threshold voltage of the SOI wafer, as compared to a semiconductor device integrated on a general silicon wafer.
FIG. 1 is a cross-sectional view showing a DRAM cell implemented on a conventional SOI wafer. In FIG. 1, a SOI wafer 10 is configured of a stacked structure including a silicon substrate 1, a buried oxide layer 2, and a silicon layer 3. A device isolating layer 11, defining an activation region on the silicon layer 3 of the SOI wafer 10, is formed to adjoin the buried oxide layer 2. A gate 12 is formed on a upper surface of the activation region of the silicon layer 3 and source/drain regions 13a, 13b are formed in the silicon layer 3 on both sides of the gate 12 to adjoin the buried oxide layer 2.
In a DRAM cell implemented on the SOI wafer 10, holes and electrons are captured by a floating body corresponding to a channel region below the gate 12 so that data can be stored.
For example, as shown in FIG. 2a, a store state “1” may be illustrated where lots of holes are in the floating body. As shown in FIG. 2b, a store state “0” may be illustrated where less holes or lots of electrons are in the floating body. In a read state, a higher sensing current flows through a 1-transistor type cell in a store state “1” than in a store state “0”.
For such a DRAM cell implemented on the conventional SOI wafer as described above, a need exists for a method capable of efficiently writing and reading data in a low voltage state and a method capable of stably driving a multi-bit operation of the 1-transistor type DRAM cell.